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MK3732-10
VCXO AND MULTIPLIER
Description
The MK3732-10 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by 115 ppm. Using ICS' analog/digital Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 27 MHz pullable crystal input to produce three output clocks. ICS manufactures the largest variety of MPEG clock synthesizers for all applications. Consult ICS to eliminate VCXOs, crystals, and oscillators from your board.
Features
* * * * * *
Packaged in 16 pin SOIC Replaces a VCXO and oscillator Contains popular multiplier values Uses an inexpensive 27 MHz pullable crystal Includes popular audio frequencies from 27 MHz On-chip patented VCXO with pull range of 230 ppm (115 ppm) minimum
* VCXO tuning voltage of 0 to 3.3 V * Advanced, low power, sub-micron CMOS process * Operating voltage of 3.3 V
Block Diagram
VDD
2
PDCLK3
S3:S0 VIN X1 16 - 28 MHz Pullable Crystal
4
PLL/Clock Synthesis Circuitry
CLK
REF/2 Voltage Controlled Crystal Oscillator
2
/2 REF
X2
GND
OE (all outputs)
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MK3732-10 VCXO AND MULTIPLIER
Pin Assignment
X1 VDD VDD VIN GND GND S3 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 OE S1 REF/2 REF CLK3 S0 PDCLK3
16 Pin (150 mil) SOIC
Clock Select Table
S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16 - 28 16 - 28 16 - 28 16 - 27 27 27 27 27 REF/2 REF/2 REF/2 REF/2 13.5 13.5 13.5 13.5 Input 16 - 28 16 - 28 16 - 28 16 - 28 16 - 28 16 - 28 16 - 28 CLK1 REF/2 REF/2 REF/2 REF/2 REF/2 REF/2 REF/2 CLK2 REF REF REF REF REF REF REF TEST REF REF REF REF 27 27 27 27 64 - 112 80 - 140 85 - 150 96 - 162 11.289 12.288 8.192 24.576 x4 x5 x5.333 x6 N/A N/A N/A N/A CLK3 20 - 35 21 - 37.5 24 - 42 32 - 56 40 - 70 42 - 75 48 - 84 Multiplier x1.25 x1.333 x1.5 x2 x2.5 x2.667 x3
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MK3732-10 VCXO AND MULTIPLIER
Pin Descriptions
Pin Number
1 2-3 4 5-6 7 8 9 10 11 12 13 14 15 16
Pin Name
XI VDD VIN GND S3 S2 PDCLK3 S0 CLK3 REF REF/2 S1 OE X2
Pin Type
XI Power Input Power Input Input Input Input Output Output Output Input Input XO Connect to +3.3 V.
Pin Description
Crystal connection. Connect to a pullable of 16 to 28 MHz cyrstal. Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. Connect to ground. Select input #3. Selects outputs per table above. Internal pull-up resistor. Select input #2. Selects outputs per table above. Internal pull-up resistor. Power down for CLK3. Select input #0. Selects outputs per table above. Internal pull-up resistor. PLL output clock that is either a multiple of the input or an audio clock. See table above. Buffered VCXO reference clock output. Matches crystal frequency. Reference clock output divided by two. Select input #1. Selects outputs per table above. Internal pull-up resistor. Output enable. Tri-states outputs when low. Internal pull-up resistor. Crystal connection. Connect to a pullable 16 to 28 MHz crystal.
Pin Descriptions
The MK3732-10 requires a minimum number of external components for proper operation.
Quartz Crystal
The MK3732-10 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its "cut" and by the load capacitors connected to it. The MK3732-10 incorporates on-chip variable load capacitors that "pull" (change) the frequency of the crystal. The crystal specified for use with the MK3732-10 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF.
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 2 and 5 and pins 3 and 6, as close to the MK3732-10 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs (CLK, pin 5) and the loads are over 1 inch, series termination should be used. To series terminate a 50 trace (a commonly used trace impedance) place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
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MK3732-10 VCXO AND MULTIPLIER
Recommended Crystal Parameters: Initial Accuracy at 25C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance
20 ppm 30 ppm 20 ppm 14 pf 7 pF Max 250 Max 35 Max
1. Connect VDD to 3.3V. Connect pin 3 to the second power supply. Adjust the voltage on pin 3 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 3 to 3.3V. Measure and record the frequency of the same output. To calculate the centering error:
6 ( f 3.3 ( 3.0 )V - f t arg et ) + ( f 0V - f t arg et ) Error = 10 x --------------------------------------------------------------------------------------- - error xtal f t arg et
The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3732-10. There should be no via's between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05.
Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than 25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: External Capacitor = 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25ppm).
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors:
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MK3732-10 VCXO AND MULTIPLIER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3732-10. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Soldering Temperature 7V
Rating
-0.5V to VDD+0.5V 0 to +70C -65 to +150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Reference crystal parameters
Min.
0 +3.15
Typ.
3.3
Max.
+70 +3.45
Units
C V
Refer to pages 3 - 4
DC Electrical Characteristics
VDD=3.3V 5% , Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage (CMOS Level) Operating Supply Current Short Circuit Current
Symbol
VDD VIH VIL VIH VIL VOH VOL VOH IDD
Conditions
X1 pin, clock in Non VCXO mode X1 pin, clock in Non VCXO mode
Min.
3.15 (VDD/2)+1
Typ.
3.3
Max.
3.45
Units
V V
(VDD/2)-1 2 0.8
V V V V V V
IOH = -12 mA IOL = 12 mA IOH = -4 mA No Load Each output
2.4 0.4 -0.5 19 50
mA mA
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MK3732-10 VCXO AND MULTIPLIER
Parameter
Input Capacitance Frequency Synthesis Error VIN, VCXO Control Voltage
Symbol
CIN V IA
Conditions
S2:S0, OE All clocks
Min.
Typ.
5
Max.
0
Units
pF ppm V
0
3.3
AC Electrical Characteristics
VDD = 3.3V 5%, Ambient Temperature 0 to +70 C, unless stated otherwise
Parameter
Input Crystal Frequency Output Clock Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter Output pullability 0V < VIN < 3.3V, Note 1 115
Symbol
fIN fOUT
Conditions
Min.
16 8
Typ.
27 1.5 1.5
Max. Units
28 162 MHz MHz ns ns 60 % ps ppm
0.8 to 2.0V 2.0 to 0.8V at VDD/2 40
350
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on pages 3-4.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 115 105 58
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram
MK3732-10S $$###### YYWW
Notes: 1. ###### is the lot number 2. YYWW is the last two digits of the year and the week number that the part was assembled
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MK3732-10 VCXO AND MULTIPLIER
Package Outline and Package Dimensions (16 pin SOIC)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol Min Max Inches Min Max
16
E INDEX AREA
H
12 D
A A1 B C D E e H h L
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
h x 45 C
-Ce
B SEATING PLANE
.10 (.004)
L
C
Ordering Information
Part / Order Number (Note 1)
MK3732-10S MK3732-10STR
Marking
MK3732-10S MK3732-10S
Shipping packaging
Tubes Tape and Reel
Package
16 pin SOIC 16 pin SOIC
Temperature
0 to +70 C 0 to +70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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